We investigate the electrical characteristics according to changing temperature on trap distribution in the energy gap of grain boundary (GB) and interface trap density (D(it)) between polycrystalline-silicon (poly-Si) channel and tunnel oxide in Vertical NAND (VNAND) flash cell with poly-Si channel. We confirmed that there are two factors changing GB potential barrier height such as trap distribution in GB and D(it) using technology computer-aided design (TCAD) simulation. Also, we found that the electrical characteristics according to changing temperature are significantly dependent on height and position of GB potential barrier in VNAND flash cell with poly-Si channel. We expect that it is required to develop more accurate extraction method for trap distribution in each GB and D(it) for better understanding temperature dependence of electrical characteristics in VNAND Flash cell.
Keywords: 3D Verticle NAND Flash Cell; Poly-Si Channel; Grain Boundary; Trap Distribution; Interface Trap.