Four-Bits-Per-Cell Operation in an HfO2 -Based Resistive Switching Device

Gun Hwan Kim; Hyunsu Ju; Min Kyu Yang; Dong Kyu Lee; Ji Woon Choi; Jae Hyuck Jang; Sang Gil Lee; Ik Su Cha; Bo Keun Park; Jeong Hwan Han; Taek-Mo Chung; Kyung Min Kim; Cheol Seong Hwang; Young Kuk Lee

doi:10.1002/smll.201701781

Four-Bits-Per-Cell Operation in an HfO₂ -Based Resistive Switching Device

Small. 2017 Oct;13(40). doi: 10.1002/smll.201701781. Epub 2017 Aug 30.

Authors

Affiliations

¹ Center for Thin-Film Materials, Korea Research Institute of Chemical Technology (KRICT), 141 Gajeong-Ro, Yuseong-Gu, Daejeon, 34114, Republic of Korea.
² Center for Opto-Electronic Materials and Devices, Post-Silicon Semiconductor Institute, Korea Institute of Science and Technology (KIST), Seoul, 02792, Republic of Korea.
³ School of Electrical and Electronics Engineering, Yonsei University, 262 Seongsanno, Seodaemun-gu, Seoul, 120-749, Republic of Korea.
⁴ Department of Materials Science and Engineering, Yonsei University, 262 Seongsanno, Seodaemun-gu, Seoul, 120-749, Republic of Korea.
⁵ Center for Electron Microscopy Research, Korea Basic Science Institute (KBSI), 169-148 Gwahak-ro, Yuseong-gu, Daejeon, 34133, Republic of Korea.
⁶ Hewlett Packard Labs, Hewlett Packard Enterprise, Palo Alto, CA, 94304, USA.
⁷ Department of Materials Science and Engineering and Inter-University Semiconductor Research Center, College of Engineering, Seoul National University, Seoul, 08826, Republic of Korea.

PMID: 28857422
DOI: 10.1002/smll.201701781

Abstract

The quadruple-level cell technology is demonstrated in an Au/Al₂ O₃ /HfO₂ /TiN resistance switching memory device using the industry-standard incremental step pulse programming (ISPP) and error checking/correction (ECC) methods. With the highly optimistic properties of the tested device, such as self-compliance and gradual set-switching behaviors, the device shows 6σ reliability up to 16 states with a state current gap value of 400 nA for the total allowable programmed current range from 2 to 11 µA. It is demonstrated that the conventional ISPP/ECC can be applied to such resistance switching memory, which may greatly contribute to the commercialization of the device, especially competitively with NAND flash. A relatively minor improvement in the material and circuitry may enable even a five-bits-per-cell technology, which can hardly be imagined in NAND flash, whose state-of-the-art multiple-cell technology is only at three-level (eight states) to this day.

Keywords: HfO2; error checking/correction (ECC) algorithm; incremental step pulse programming (ISPP); quadruple-level cell (QLC); resistive switching (RS) memory.

Publication types

Research Support, Non-U.S. Gov't