The charge-trapping memory devices with a structure Pt/Al2O3/(Ta2O5) x (TiO2) 1-x /Al2O3/p-Si (x = 0.9, 0.75, 0.5, 0.25) were fabricated by using rf-sputtering and atomic layer deposition techniques. A special band alignment between (Ta2O5) x (TiO2) 1-x and Si substrate was designed to enhance the memory performance by controlling the composition and dielectric constant of the charge-trapping layer and reducing the difference of the potentials at the bottom of the conduction band between (Ta2O5) x (TiO2) 1-x and Si substrate. The memory device with a composite charge storage layer (Ta2O5) 0.5 (TiO2) 0.5 shows a density of trapped charges 3.84 × 1013/cm2 at ± 12 V, a programming/erasing speed of 1 µs at ± 10 V, a 8% degradation of the memory window at ± 10 V after 104 programming/erasing cycles and a 32% losing of trapped charges after ten years. The difference among the activation energies of the trapped electrons in (Ta2O5) x (TiO2) 1-x CTM devices indicates that the retention characteristics are dominated by the difference of energy level for the trap sites in each TTO CTM device.