A robust integrated power splitter based on a silicon-on-insulator adiabatic coupler configuration is demonstrated. The power separation is achieved by a slow and simultaneous change of phase and coupling constants. The geometrical parameters of the device are determined thanks to a metamodel-based iterative optimization strategy. Solving the multiple parameter problem together with a realistic bandwidth constraint provides a clear improvement of the power splitting stability. The robustness is confirmed experimentally on a single device and at the wafer scale.