Nowadays, III-V compound semiconductor nanowires (NWs) have attracted extensive research interest because of their high carrier mobility favorable for next-generation electronics. However, it is still a great challenge for the large-scale synthesis of III-V NWs with well-controlled and uniform morphology as well as reliable electrical properties, especially on the low-cost noncrystalline substrates for practical utilization. In this study, high-density GaAs NWs with lengths >10 μm and uniform diameter distribution (relative standard deviation σ ∼ 20%) have been successfully prepared by annealing the Au catalyst films (4-12 nm) in air right before GaAs NW growth, which is in distinct contrast to the ones of 2-3 μm length and widely distributed of σ ∼ 20-60% of the conventional NWs grown by the H2-annealed film. This air-annealing process is found to stabilize the Au nanoparticle seeds and to minimize Ostwald ripening during NW growth. Importantly, the obtained GaAs NWs exhibit uniform p-type conductivity when fabricated into NW-arrayed thin-film field-effect transistors (FETs). Moreover, they can be integrated with an n-type InP NW FET into effective complementary metal oxide semiconductor inverters, capable of working at low voltages of 0.5-1.5 V. All of these results explicitly demonstrate the promise of these NW morphology and electrical property controls through the catalyst engineering for next-generation electronics.
Keywords: CMOS inverter; GaAs nanowire; diameter control; electronic property; oxygen.