Although the various effects of strain on silicon are subject of intensive research since the 1950s the physical background of anomalous piezoresistive effects in Si nanowires (NWs) is still under debate. Recent investigations concur in that due to the high surface-to-volume ratio extrinsic surface related effects superimpose the intrinsic piezoresistive properties of nanostructures. To clarify this interplay of piezoresistive effects and stress related surface potential modifications, we explored a particular tensile straining device (TSD) with a monolithic embedded vapor-liquid-solid (VLS) grown Si NW. Integrating the suspended NW in a gate all around (GAA) field effect transistor (FET) configuration with a transparent gate stack enables optical and field modulated electrical characterization under high uniaxial tensile strain applied along the ⟨111⟩ Si NW growth direction. A model based on stress-induced carrier mobility change and surface charge modulation is proposed to interpret the actual piezoresistive behavior of Si NWs. By controlling the nature and density of surface states via passivation the "true" piezoresistance of the NWs is found to be comparable with that of bulk Si. This demonstrates the indispensability of application-specific NW surface conditioning and the modulation capability of Si NWs properties for sensor applications.
Keywords: Silicon; VLS growth; nanowire; piezoresistance; surface doping.