Design of high speed and low offset dynamic latch comparator in 0.18 µm CMOS process

PLoS One. 2014 Oct 9;9(10):e108634. doi: 10.1371/journal.pone.0108634. eCollection 2014.

Abstract

The cross-coupled circuit mechanism based dynamic latch comparator is presented in this research. The comparator is designed using differential input stages with regenerative S-R latch to achieve lower offset, lower power, higher speed and higher resolution. In order to decrease circuit complexity, a comparator should maintain power, speed, resolution and offset-voltage properly. Simulations show that this novel dynamic latch comparator designed in 0.18 µm CMOS technology achieves 3.44 mV resolution with 8 bit precision at a frequency of 50 MHz while dissipating 158.5 µW from 1.8 V supply and 88.05 µA average current. Moreover, the proposed design propagates as fast as 4.2 nS with energy efficiency of 0.7 fJ/conversion-step. Additionally, the core circuit layout only occupies 0.008 mm2.

Publication types

  • Research Support, Non-U.S. Gov't

MeSH terms

  • Electronics, Medical / instrumentation
  • Equipment Design / instrumentation*
  • Equipment Failure Analysis / instrumentation
  • Semiconductors
  • Signal Processing, Computer-Assisted / instrumentation*
  • Transistors, Electronic

Grants and funding

The authors would like to express sincere gratitude to the MIMOS Berhad and Universiti Kebangsaan Malaysia for the collaborative research grant eScienceFund and the research university grant DLP-2013-016 and UKM-AP-ICT-20-2010. The funders had no role in study design, data collection and analysis, decision to publish, or preparation of the manuscript.