Time-to-digital converters (TDC) implemented in a single field-programmable gate array (FPGA) chip which overcome the difficulties found in other FPGA-based TDCs are proposed in this paper. Emphasis is placed on the construction of two delay lines with a good delay consistency, as well as a minimum delay difference by which the measurement resolution can be improved and measurement error can be reduced. A modified vernier delay line structure is introduced which abandoned special delay elements and directly used FPGA internal routing resources to generate the cell delay. To get a good consistency for the system, manual placement and manual routing are used to standardize the delays. The resolution of the system is 9 ps and the standard deviation is less than 1 least significant bit (LSB) within the whole measurement range. The corrected differential nonlinearity is as low as 0.11 LSB. Experiments showed that the proposed system features high accuracy, low cost, and high stability.