A flexible acquisition cycle for incompletely defined fieldbus protocols

Vasile-Gheorghita Gaitan; Nicoleta-Cristina Gaitan; Ioan Ungurean

doi:10.1016/j.isatra.2014.02.006

A flexible acquisition cycle for incompletely defined fieldbus protocols

ISA Trans. 2014 May;53(3):776-86. doi: 10.1016/j.isatra.2014.02.006. Epub 2014 Mar 17.

Authors

Vasile-Gheorghita Gaitan¹, Nicoleta-Cristina Gaitan², Ioan Ungurean³

Affiliations

¹ Stefan cel Mare University of Suceava, Universitatii Street no. 13, 720229 Suceava, Romania. Electronic address: gaitan@eed.usv.ro.
² Stefan cel Mare University of Suceava, Universitatii Street no. 13, 720229 Suceava, Romania. Electronic address: cristinag@eed.usv.ro.
³ Stefan cel Mare University of Suceava, Universitatii Street no. 13, 720229 Suceava, Romania. Electronic address: ioanu@eed.usv.ro.

PMID: 24650922
DOI: 10.1016/j.isatra.2014.02.006

Abstract

Real time data-acquisition from fieldbuses strongly depends on the network type and protocol used. Currently, there is an impressive number of fieldbuses, some of them are completely defined and others are incompletely defined. In those from the second category, the time variable, the main element in real-time data acquisition, does not appear explicitly. Examples include protocols such as Modbus ASCII/RTU, M-bus, ASCII character-based, and so on. This paper defines a flexible acquisition cycle based on the Master-Slave architecture that can be implemented on a Master station, called a Base Station Gateway (BSG). The BSG can add a timestamp for temporal location of data. It also presents a possible extension for the Modbus protocol, developed as simple and low cost solution based on existing hardware.

Keywords: Data acquisition; Field buses; Protocols; Real time systems; Temporal coherence.