3D-transistor array based on horizontally suspended silicon nano-bridges grown via a bottom-up technique

Abstract

Integrated surround-gate field-effect-transistors enabled by bottom-up synthesis of nano-bridges are demonstrated. Horizontally oriented silicon nano-bridge devices are fabricated avoiding the rigorous processes for aligning and contacting nanowires grown via a bottom-up technique. Evaluation of electrical properties and a memory device application of the transistors are presented.

Keywords: VLS; bottom-up; bridge; field effect transistor; memory; nanowire; silicon; surround gate.