Silicon nanowire (SiNW) field-effect transistors have been fabricated by oxidation scanning probes and electron beam lithographies. The analysis and comparison of the electron mobility and subthreshold swing shows that the device performance is not affected by the top-down fabrication method. The two methods produce silicon nanowire transistors with similar electrical features, although oxidation scanning probe lithography generates nanowires with smaller channel widths. The values of the electron mobility and the subthreshold swing, 200 cm(2) V(-1) s(-1) and 500 mV dec(-1), respectively, are similar to those obtained from bottom-up methods. The compatibility of top-down methods with CMOS (complementary metal-oxide-semiconductor) procedures, the good electrical properties of the nanowire devices and the potential for making sub-10 nanowires, in particular by using oxidation scanning probe lithography, make those methods attractive for device fabrication.