Effect of ashing conditions and optimization of nano process integration in copper/porous low-k nano-interconnects

J Nanosci Nanotechnol. 2012 Nov;12(11):8401-6. doi: 10.1166/jnn.2012.6671.

Abstract

We report the optimization of ashing conditions and the process integration of a chemical vapor deposition (CVD) ultra low-k (k = 2.2) organosilicate (OSG) dielectric in a top hard mask damascene structure. The N2/H2 ash showed the lowest resistance-capacitance (RC) product and a dual top hard mask approach for dual damascene processing was built, using 200 nm SiC/50 nm SiO2 as the hard mask. This CVD low-k material had no low-k voiding, unlike other spin-on dielectric (SOD) low-k materials. The presence of the densified layer around the trench during the ashing process could improve the precursor penetration during the CVD barrier metal deposition process.

Publication types

  • Research Support, Non-U.S. Gov't

MeSH terms

  • Copper / chemistry*
  • Crystallization / methods*
  • Electric Conductivity
  • Macromolecular Substances / chemistry
  • Materials Testing
  • Metal Nanoparticles / chemistry*
  • Metal Nanoparticles / ultrastructure*
  • Molecular Conformation
  • Particle Size
  • Porosity
  • Surface Properties

Substances

  • Macromolecular Substances
  • Copper