Modern microelectrode arrays acquire neural signals from hundreds of neurons in parallel that are subsequently processed for spike sorting. It is important to identify, extract, and transmit appropriate features that allow accurate spike sorting while using minimum computational resources. This paper describes a new set of spike sorting features, explicitly framed to be computationally efficient and shown to outperform principal component analysis (PCA)-based spike sorting. A hardware friendly architecture, feasible for implantation, is also presented for detecting neural spikes and extracting features to be transmitted for off chip spike classification. The proposed feature set does not require any off-chip training, and requires about 5% of computations as compared to the PCA-based features for the same classification accuracy, tested for spike trains with a broad range of signal-to-noise ratio. Our simulations show a reduction of required bandwidth to about 2% of original data rate, with an average classification accuracy of greater than 94% at a typical signal to noise ratio of 5 dB.