Yttria-stabilized zirconia (YSZ) layers of various thicknesses were designed and introduced before Pr0.7Ca0.3MnO3 (PCMO) film was deposited on W bottom electrodes with a submicron via-hole structure. By changing the thickness of the YSZ barrier layer (3, 5, 9, and 13 nm), a tunable memory window can be realized while low power consumption (P(max) < 4 microW) is maintained. Resistive switching (RS) in a Pt/PCMO/YSZ/W stack with a thin YSZ layer can be ascribed to an oxidation/reduction reaction caused by a ring-type PCMO/W contact, while RS with a thick YSZ layer may be related to oxygen migration across the YSZ layer between the PCMO film and the W bottom electrode and the increase (decrease) of the effective tunnel barrier height of the YSZ layer. Excellent RS behavior characteristics, such as a large R(HRS)/R(LRS) ratio (> 10(3)), die-to-die uniformity, sweeping endurance, and a retention time of more than 10(3) s, can be obtained by optimizing the thickness of YSZ layer.