We discuss the origin of an additional dip other than the charge neutrality point observed in the transfer characteristics of graphene-based field-effect transistors with a Si/SiO2 substrate used as the back-gate. The double dip is proved to arise from charge transfer between the graphene and the metal electrodes, while charge storage at the graphene/SiO2 interface can make it more evident. Considering a different Fermi energy from the neutrality point along the channel and partial charge pinning at the contacts, we propose a model which explains all the features observed in the gate voltage loops. We finally show that the double dip enhanced hysteresis in the transfer characteristics can be exploited to realize graphene-based memory devices.