The successful implementation of nanowire (NW) based field-effect transistors (FET) critically depends on quantitative information about the carrier distribution inside such devices. Therefore, we have developed a method based on high-vacuum scanning spreading resistance microscopy (HV-SSRM) which allows two-dimensional (2D) quantitative carrier profiling of fully integrated silicon NW-based tunnel-FETs (TFETs) with 2 nm spatial resolution. The key elements of our characterization procedure are optimized NW cleaving and polishing steps, the use of in-house fabricated ultra-sharp diamond tips, measurements in high vacuum and a dedicated quantification procedure accounting for the Schottky-like tip-sample contact affected by surface states. In the case of the implanted TFET source regions we find a strong NW diameter dependence of conformality, junction abruptness and gate overlap, quantitatively in agreement with process simulations. In contrast, the arsenic doped drain regions reveal an unexpected NW diameter dependent dopant deactivation. The observed lower drain doping for smaller diameters is reflected in the device characteristics by lower TFET off-currents, as measured experimentally and confirmed by device simulations.