We present a novel additive process, which allows the spatially controlled integration of nanoparticles (NPs) inside silicon surfaces. The NPs are placed between a conductive stamp and a silicon surface; by applying a bias voltage a SiO(2) layer grows underneath the stamp protrusions, thus embedding the particles. We report the successful nanoembedding of CoFe(2)O(4) nanoparticles patterned in lines, grids and logic structures.