A sub-picojoule-per-bit CMOS photonic receiver for densely integrated systems

Opt Express. 2010 Jan 4;18(1):204-11. doi: 10.1364/OE.18.000204.

Abstract

We report ultra-low-power (690fJ/bit) operation of an optical receiver consisting of a germanium-silicon waveguide detector intimately integrated with a receiver circuit and embedded in a clocked digital receiver. We show a wall-plug power efficiency of 690microW/Gbps for the photonic receiver made of a 130nm SOI CMOS Ge waveguide detector integrated to a 90nm Si CMOS receiver circuit. The hybrid CMOS photonic receiver achieved a sensitivity of -18.9dBm at 5Gbps for BER of 10(-12). Enabled by a unique low-overhead bias refresh scheme, the receiver operates without the need for DC balanced transmission. Small signal measurements of the CMOS Ge waveguide detector showed a 3dB bandwidth of 10GHz at 1V of reverse bias, indicating that further increases in transmission rate and reductions of energy-per-bit will be possible.

MeSH terms

  • Equipment Design
  • Equipment Failure Analysis
  • Optical Devices*
  • Photometry / instrumentation*
  • Semiconductors*
  • Signal Processing, Computer-Assisted / instrumentation*
  • Systems Integration
  • Telecommunications / instrumentation*