We demonstrate a fabrication method for high-performance field-effect transistors (FETs) based on dry-processed random single-walled carbon nanotube networks (CNTNs) deposited at room temperature. This method is an advantageous alternative to solution-processed and direct CVD grown CNTN FETs, which allows using various substrate materials, including heat-intolerant plastic substrates, and enables an efficient, density-controlled, scalable deposition of as-produced single-walled CNTNs on the substrate directly from the aerosol (floating catalyst) synthesis reactor. Two types of thin film transistor (TFT) structures were fabricated to evaluate the FET performance of dry-processed CNTNs: bottom-gate transistors on Si/SiO2 substrates and top-gate transistors on polymer substrates. Devices exhibited on/off ratios up to 10(5) and field-effect mobilities up to 4 cm(2) V(-1) s(-1). The suppression of hysteresis in the bottom-gate device transfer characteristics by means of thermal treatment in vacuum and passivation by an atomic layer deposited Al(2)O(3) film was investigated. A 32 nm thick Al(2)O(3) layer was found to be able to eliminate the hysteresis.