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zhucheng pan
(4 results)?
Impact of Stress and Dimension on Nanosheet Deformation during Channel Release of Gate-All-Around Device.
Micromachines (Basel). 2023 Mar 7;14(3):611. doi: 10.3390/mi14030611.
Micromachines (Basel). 2023.
PMID: 36985018
Free PMC article.
A Buried Thermal Rail (BTR) Technology to Improve Electrothermal Characteristics of Complementary Field-Effect Transistor (CFET).
Pan Z, Liu T, Yang J, Chen K, Xu S, Wu C, Xu M, Zhang DW.
Pan Z, et al.
Micromachines (Basel). 2023 Sep 7;14(9):1751. doi: 10.3390/mi14091751.
Micromachines (Basel). 2023.
PMID: 37763913
Free PMC article.
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A Novel Scheme for Full Bottom Dielectric Isolation in Stacked Si Nanosheet Gate-All-Around Transistors.
Yang J, Huang Z, Wang D, Liu T, Sun X, Qian L, Pan Z, Xu S, Wang C, Wu C, Xu M, Zhang DW.
Yang J, et al. Among authors: pan z.
Micromachines (Basel). 2023 May 24;14(6):1107. doi: 10.3390/mi14061107.
Micromachines (Basel). 2023.
PMID: 37374692
Free PMC article.
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