A Reliability Investigation of VDMOS Transistors: Performance and Degradation Caused by Bias Temperature Stress

Micromachines (Basel). 2024 Apr 5;15(4):503. doi: 10.3390/mi15040503.

Abstract

This study aimed to comprehensively understand the performance and degradation of both p- and n-channel vertical double diffused MOS (VDMOS) transistors under bias temperature stress. Conducted experimental investigations involved various stress conditions and annealing processes to analyze the impacts of BT stress on the formation of oxide trapped charge and interface traps, leading to threshold voltage shifts. Findings revealed meaningful threshold voltage shifts in both PMOS and NMOS devices due to stresses, and the subsequent annealing process was analyzed in detail. The study also examined the influence of stress history on self-heating behavior under real operating conditions. Additionally, the study elucidated the complex correlation between stress-induced degradation and device reliability. The insights contribute to optimizing the performance and permanence of VDMOS transistors in practical applications, advancing semiconductor technology. This study underscored the importance of considering stress-induced effects on device reliability and performance in the design and application of VDMOS transistors.

Keywords: NBTI; VDMOS; reliability; responsible mechanisms; self-heating.

Grants and funding

This work was supported by the Serbian Ministry of Science, Technological Development and Innovation [grant number 451-03-65/2024-03/200102]. Part of this project was also realized through the project of the Bulgarian National Science Fund, project KP-06-H37/32. Part of results published in this manuscript were obtained during the realization of project SPS G5974—“High-k Dielectric RADFET for Detection of RN Treats”.