A Multi-Resolution Mode CMOS Image Sensor with a Novel Two-Step Single-Slope ADC for Intelligent Surveillance Systems

Daehyeok Kim; Minkyu Song; Byeongseong Choe; Soo Youn Kim

doi:10.3390/s17071497

A Multi-Resolution Mode CMOS Image Sensor with a Novel Two-Step Single-Slope ADC for Intelligent Surveillance Systems

Sensors (Basel). 2017 Jun 25;17(7):1497. doi: 10.3390/s17071497.

Authors

Daehyeok Kim¹, Minkyu Song², Byeongseong Choe³, Soo Youn Kim⁴

Affiliations

¹ Department of Semiconductor Science, Dongguk University-Seoul, Seoul 04620, Korea. dh7423@dongguk.edu.
² Department of Semiconductor Science, Dongguk University-Seoul, Seoul 04620, Korea. mksong@dongguk.edu.
³ Department of Information and Telecommunication Engineering, Dongguk University-Seoul, Seoul 04620, Korea. bchoe@dongguk.edu.
⁴ Department of Semiconductor Science, Dongguk University-Seoul, Seoul 04620, Korea. sooyoun@dongguk.edu.

Abstract

In this paper, we present a multi-resolution mode CMOS image sensor (CIS) for intelligent surveillance system (ISS) applications. A low column fixed-pattern noise (CFPN) comparator is proposed in 8-bit two-step single-slope analog-to-digital converter (TSSS ADC) for the CIS that supports normal, 1/2, 1/4, 1/8, 1/16, 1/32, and 1/64 mode of pixel resolution. We show that the scaled-resolution images enable CIS to reduce total power consumption while images hold steady without events. A prototype sensor of 176 × 144 pixels has been fabricated with a 0.18 μm 1-poly 4-metal CMOS process. The area of 4-shared 4T-active pixel sensor (APS) is 4.4 μm × 4.4 μm and the total chip size is 2.35 mm × 2.35 mm. The maximum power consumption is 10 mW (with full resolution) with supply voltages of 3.3 V (analog) and 1.8 V (digital) and 14 frame/s of frame rates.

Keywords: CMOS image sensor; fixed pattern noise; intelligent surveillance system (ISS); low power consumption; multi-mode pixel resolution; two-step single-slope ADC.