Monolithic 3D integration of 2D materials-based electronics towards ultimate edge computing solutions

Ji-Hoon Kang; Heechang Shin; Ki Seok Kim; Min-Kyu Song; Doyoon Lee; Yuan Meng; Chanyeol Choi; Jun Min Suh; Beom Jin Kim; Hyunseok Kim; Anh Tuan Hoang; Bo-In Park; Guanyu Zhou; Suresh Sundaram; Phuong Vuong; Jiho Shin; Jinyeong Choe; Zhihao Xu; Rehan Younas; Justin S Kim; Sangmoon Han; Sangho Lee; Sun Ok Kim; Beomseok Kang; Seungju Seo; Hyojung Ahn; Seunghwan Seo; Kate Reidy; Eugene Park; Sungchul Mun; Min-Chul Park; Suyoun Lee; Hyung-Jun Kim; Hyun S Kum; Peng Lin; Christopher Hinkle; Abdallah Ougazzaden; Jong-Hyun Ahn; Jeehwan Kim; Sang-Hoon Bae

doi:10.1038/s41563-023-01704-z

Monolithic 3D integration of 2D materials-based electronics towards ultimate edge computing solutions

Nat Mater. 2023 Dec;22(12):1470-1477. doi: 10.1038/s41563-023-01704-z. Epub 2023 Nov 27.

Authors

Ji-Hoon Kang^#^{1

2

3}, Heechang Shin^#⁴, Ki Seok Kim^#^{1

2}, Min-Kyu Song^#^{1

2}, Doyoon Lee^{1

2}, Yuan Meng⁵, Chanyeol Choi^{2

6}, Jun Min Suh^{1

2}, Beom Jin Kim⁴, Hyunseok Kim^{1

2}, Anh Tuan Hoang⁴, Bo-In Park^{1

2}, Guanyu Zhou⁷, Suresh Sundaram^{8

9}, Phuong Vuong⁹, Jiho Shin^{1

2}, Jinyeong Choe⁴, Zhihao Xu¹⁰, Rehan Younas⁷, Justin S Kim¹⁰, Sangmoon Han⁵, Sangho Lee^{1

2}, Sun Ok Kim⁵, Beomseok Kang^{1

2}, Seungju Seo^{1

2}, Hyojung Ahn^{11

12}, Seunghwan Seo^{1

2}, Kate Reidy¹³, Eugene Park¹³, Sungchul Mun^{14

15}, Min-Chul Park¹⁶, Suyoun Lee¹⁶, Hyung-Jun Kim¹⁶, Hyun S Kum⁴, Peng Lin^{1

2

17}, Christopher Hinkle⁷, Abdallah Ougazzaden^{8

9}, Jong-Hyun Ahn¹⁸, Jeehwan Kim^{19

20

21}, Sang-Hoon Bae^{22

23}

Affiliations

¹ Department of Mechanical Engineering, Massachusetts Institute of Technology, Cambridge, MA, USA.
² Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MA, USA.
³ Department of Electronic Engineering, Inha University, Incheon, Republic of Korea.
⁴ School of Electrical and Electronic Engineering, Yonsei University, Seoul, Republic of Korea.
⁵ Department of Mechanical Engineering and Materials Science, Washington University in Saint Louis, Saint Louis, MO, USA.
⁶ Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA, USA.
⁷ Department of Electrical Engineering, University of Notre Dame, Notre Dame, IN, USA.
⁸ School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA.
⁹ CNRS, Georgia Tech - CNRS IRL 2958, GT-Europe, Metz, France.
¹⁰ Institute of Materials Science and Engineering, Washington University in Saint Louis, Saint Louis, MO, USA.
¹¹ Future Innovation Research Center, Korea Aerospace Research Institute, Daejeon, Republic of Korea.
¹² Aerospace System Engineering, University of Science and Technology, Daejeon, Republic of Korea.
¹³ Department of Materials Science and Engineering, Massachusetts Institute of Technology, Cambridge, MA, USA.
¹⁴ Department of Industrial Engineering, Jeonju University, Jeonju, Republic of Korea.
¹⁵ Convergence Institute of Human Data Technology, Jeonju University, Jeonju, Republic of Korea.
¹⁶ Post-Silicon Semiconductor Institute, Korea Institute of Science and Technology, Seoul, Republic of Korea.
¹⁷ College of Computer Science and Technology, Zhejiang University, Hangzhou, China.
¹⁸ School of Electrical and Electronic Engineering, Yonsei University, Seoul, Republic of Korea. ahnj@yonsei.ac.kr.
¹⁹ Department of Mechanical Engineering, Massachusetts Institute of Technology, Cambridge, MA, USA. jeehwan@mit.edu.
²⁰ Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MA, USA. jeehwan@mit.edu.
²¹ Department of Materials Science and Engineering, Massachusetts Institute of Technology, Cambridge, MA, USA. jeehwan@mit.edu.
²² Department of Mechanical Engineering and Materials Science, Washington University in Saint Louis, Saint Louis, MO, USA. sbae22@wustl.edu.
²³ Institute of Materials Science and Engineering, Washington University in Saint Louis, Saint Louis, MO, USA. sbae22@wustl.edu.

^# Contributed equally.

PMID: 38012388
DOI: 10.1038/s41563-023-01704-z

Abstract

Three-dimensional (3D) hetero-integration technology is poised to revolutionize the field of electronics by stacking functional layers vertically, thereby creating novel 3D circuity architectures with high integration density and unparalleled multifunctionality. However, the conventional 3D integration technique involves complex wafer processing and intricate interlayer wiring. Here we demonstrate monolithic 3D integration of two-dimensional, material-based artificial intelligence (AI)-processing hardware with ultimate integrability and multifunctionality. A total of six layers of transistor and memristor arrays were vertically integrated into a 3D nanosystem to perform AI tasks, by peeling and stacking of AI processing layers made from bottom-up synthesized two-dimensional materials. This fully monolithic-3D-integrated AI system substantially reduces processing time, voltage drops, latency and footprint due to its densely packed AI processing layers with dense interlayer connectivity. The successful demonstration of this monolithic-3D-integrated AI system will not only provide a material-level solution for hetero-integration of electronics, but also pave the way for unprecedented multifunctional computing hardware with ultimate parallelism.

Abstract

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