Soft error mitigation and recovery of SRAM-based FPGAs using brain-inspired hybrid-grained scrubbing mechanism

Abstract

Soft error has increasingly become a critical concern for SRAM-based field programmable gate arrays (FPGAs), which could corrupt the configuration memory that stores configuration data describing the custom-designed circuit architecture. To mitigate this kind of error, this study proposes a brain-inspired hybrid-grained scrubbing mechanism consisting of fine-grained and coarse-grained scrubbing to mitigate and repair the errors as quickly as possible after an SEU occurrence. Inspired by the human brain's ability to filter out redundant and irrelevant information, we propose a mechanism that can mask invalid position information when errors occur. Compared with the scrubbing of full configuration memory, this mechanism can achieve precise error location and recovery utilizing targeted scrubbing of specific frames or modules. The effectiveness is evaluated by executing fault injection campaigns on the International Symposium on Circuits and Systems 1989 (ISCAS89) benchmark circuits and fault tolerant fast Fourier transform (FT-FFT) circuit. If upsets are detected, they will be repaired with fine-grained or coarse-grained scrubbing depending on their location. The experiment results show that this mechanism can effectively mitigate and repair single-bit upsets (SBUs) and double-bit upsets (DBUs). In addition, the mechanism is proven to be superior in error recovery time and hardware overhead compared to counterpart approaches.

Keywords: SRAM-based FPGA; brain-inspired; configuration scrubbing; hybrid-grained; single event upset (SEU).