Performance limit of all-wrapped monolayer MoS2 transistors

Wenbo Zhang; Binxi Liang; Jiachen Tang; Jian Chen; Qing Wan; Yi Shi; Songlin Li

doi:10.1016/j.scib.2023.08.014

Performance limit of all-wrapped monolayer MoS₂ transistors

Sci Bull (Beijing). 2023 Sep 30;68(18):2025-2032. doi: 10.1016/j.scib.2023.08.014. Epub 2023 Aug 9.

Authors

Wenbo Zhang¹, Binxi Liang¹, Jiachen Tang¹, Jian Chen¹, Qing Wan², Yi Shi³, Songlin Li⁴

Affiliations

¹ School of Electronic Science and Engineering, National Laboratory of Solid-State Microstructures, and Collaborative Innovation Center of Advanced Microstructures, Nanjing University, Nanjing 210023, China.
² School of Electronic Science and Engineering, National Laboratory of Solid-State Microstructures, and Collaborative Innovation Center of Advanced Microstructures, Nanjing University, Nanjing 210023, China. Electronic address: wanqing@nju.edu.cn.
³ School of Electronic Science and Engineering, National Laboratory of Solid-State Microstructures, and Collaborative Innovation Center of Advanced Microstructures, Nanjing University, Nanjing 210023, China. Electronic address: yshi@nju.edu.cn.
⁴ School of Electronic Science and Engineering, National Laboratory of Solid-State Microstructures, and Collaborative Innovation Center of Advanced Microstructures, Nanjing University, Nanjing 210023, China. Electronic address: sli@nju.edu.cn.

PMID: 37598059
DOI: 10.1016/j.scib.2023.08.014

Abstract

All-wrapped transistors consisting of two-dimensional transition-metal dichalcogenide channels are appealing candidates for post-silicon electronics. Based on the Boltzmann transport theory, here we report a comprehensive theoretical survey on the performance limits for monolayer MoS₂ transistors with three prototypical gate dielectrics (Al₂O₃, HfO₂ and BN), by including primary extrinsic charge scattering mechanisms present in practical devices. A concept of "dead space" between the dielectrics and channels is proposed and used in calculation to ameliorate the general overestimation in scattering intensity of surface optical phonons, which enables an accurate description of electronic transport behavior. Crucial device indices, including charge mobility and current density, are thoroughly analyzed for transistors at post-silicon technological nodes beyond 1 nm. The on-state current is estimated to be generally greater than 2 mA μm^-1 at channel lengths below 10 nm. The results clarify the potential benefits in performance from extremely miniaturized monolayer-channel transistors for More-Moore electronics.

Keywords: Charge mobility; Charge scattering; Charged impurities; Field-effect transistors; More-Moore electronics; Two-dimensional materials.