Accelerating GRAPPA reconstruction using SoC design for real-time cardiac MRI

Abstract

Real-time cardiac MRI is a rapidly developing area of research that has the potential to improve the diagnosis and treatment of cardiovascular diseases. However, the acquisition of high-quality real-time cardiac MR (CMR) images is challenging as it requires a high frame rate and temporal resolution. To overcome this challenge, there have been recent efforts on several approaches including hardware-based improvements and image reconstruction techniques such as compressed sensing and parallel MRI. The use of parallel MRI techniques such as GRAPPA (Generalized Autocalibrating Partial Parallel Acquisition) is a promising approach for improving the temporal resolution of MRI and expanding its applications in clinical practice. However, the GRAPPA algorithm involves a significant amount of computation, particularly for high acceleration factors and large datasets. This can result in long reconstruction times, which can limit the ability to achieve real-time imaging or high frame rates. One solution to this challenge is to use specialized hardware i.e. field-programmable gate arrays (FPGAs). In this work, a novel 32-bit floating-point FPGA-based GRAPPA accelerator is proposed with an aim to reconstruct high-quality cardiac MR images at higher frame rates, making it well suited for real-time clinical applications. The proposed FPGA-based accelerator consists of custom-designed data processing units named as dedicated computational engines (DCEs) that allow for a continuous flow of data between the calibration and synthesis stages of GRAPPA reconstruction process. This greatly increases the throughput and reduces the latency of the overall proposed system. Moreover, a high-speed memory module (DDR4-SDRAM) is integrated with the proposed architecture to store the multi-coil MR data. An on-chip quad-core ARM Cortex-A53 processor is used to manage access control information required for data transfer between the DCEs and DDR4-SDRAM. The proposed accelerator is implemented on Xilinx Zynq UltraScale + MPSoC using high-level synthesis (HLS) and hardware descriptive language (HDL) with an aim to explore the trade-offs between the reconstruction time, resource utilization and design effort. Several experiments have been performed using in-vivo cardiac datasets i.e. 18-receiver coil and 30-receiver coil to evaluate the performance of the proposed accelerator. A comparison is performed with the contemporary CPU and GPU-based GRAPPA reconstruction methods in terms of reconstruction time, frames-per-second and reconstruction accuracy (RMSE and SNR). The results show that the proposed accelerator achieves speed-up factors up to 121× and 9× as compared to the contemporary CPU-based and GPU-based GRAPPA reconstruction methods, respectively. Moreover, it has been demonstrated that the proposed accelerator can achieve reconstruction rates of up to ∼27 frames-per-second while maintaining the visual quality of the reconstructed images.

Keywords: Cardiac MRI; FPGA; GRAPPA; Hardware accelerators; Magnetic resonance imaging (MRI).