A 21.4 pW Subthreshold Voltage Reference with 0.020 %/V Line Sensitivity Using DIBL Compensation

Louis Colbach; Taekwang Jang; Youngwoo Ji

doi:10.3390/s23041862

A 21.4 pW Subthreshold Voltage Reference with 0.020 %/V Line Sensitivity Using DIBL Compensation

Sensors (Basel). 2023 Feb 7;23(4):1862. doi: 10.3390/s23041862.

Authors

Louis Colbach¹, Taekwang Jang¹, Youngwoo Ji²

Affiliations

¹ Department of Information Technology and Electrical Engineering, ETH Zurich, 8092 Zurich, Switzerland.
² Department of Electronic Engineering, Hanbat National University, Daejeon 34158, Republic of Korea.

Abstract

This paper presents an ultra-low-power voltage reference designed in 180 nm CMOS technology. To achieve near-zero line sensitivity, a two-transistor (2-T) voltage reference is biased with a current source to cancel the drain-induced barrier-lowering (DIBL) effect of the 2-T core, thus improving the line sensitivity. This compensation circuit achieves a Monte-Carlo-simulated line sensitivity of 0.035 %/V in a supply range of 0.6 to 1.8 V, while generating a reference voltage of 307.8 mV, with 21.4 pW power consumption. The simulated power supply rejection ratio (PSRR) is -54 dB at 100 Hz. It also achieves a temperature coefficient of 24.8 ppm/°C in a temperature range of -20 to 80 °C, with a projected area of 0.003 mm².

Keywords: DIBL effect; line sensitivity; subthreshold voltage reference; temperature coefficient; ultra-low-power.

Grants and funding

These results was in part supported by the “Regional Innovation Strategy (RIS)” through the National Research Foundation of Korea(NRF), funded by the Ministry of Education(MOE)(2021RIS-004). This research was in part supported by the MSIT (Ministry of Science and ICT), Korea, under the ICAN (ICT Challenge and Advanced Network of HRD) program (IITP-2023-RS-2022-00156212), supervised by the IITP (Institute of Information & Communications Technology Planning & Evaluation).