Neuron, synapse, and learning circuits inspired by the brain comprise the key components of a neuromorphic chip. In this study, we present a conductance-based analog silicon synapse circuit suitable for the implementation of reduced or multi-compartment neuron models. Compartmental models are more bio-realistic. They are implemented in neuromorphic chips aiming to mimic the electrical activities of the neuronal networks in the brain and incorporate biomimetic soma and synapse circuits. Most contemporary low-power analog synapse circuits implement bioinspired "current-based" synaptic models suited for the implementation of single-compartment point neuron models. They emulate the exponential decay profile of the synaptic current, but ignore the effect of the postsynaptic membrane potential on the synaptic current. This dependence is necessary to emulate shunting inhibition, which is thought to play important roles in information processing in the brain. The proposed circuit uses an oscillator-based resistor-type element at its output stage to incorporate this effect. This circuit is used to demonstrate the shunting inhibition phenomenon. Next, to demonstrate that the oscillatory nature of the induced synaptic current has no unforeseen effects, the synapse circuit is employed in a spatiotemporal spike pattern detection task. The task employs the adaptive spike-timing-dependent plasticity (STDP) learning rule, a bio-inspired learning rule introduced in a previous study. The mixed-signal chip is designed in a Taiwan Manufacturing Semiconductor Company 250 nm complementary metal oxide semiconductor technology node. It comprises a biomimetic soma circuit and 256 synapse circuits, along with their learning circuitries.
Keywords: adaptive STDP; biomimetic synapse circuit; neuromorphic computing; shunting inhibition; spike pattern detection; synaptic resolution; synaptic reversal potential.