A fully integrated low-dropout (LDO) regulator with improved load regulation and transient responses in 40 nm technology is presented in this paper. Combining adjustable threshold push-pull stage (ATPS) and master-slave power transistors topology, the proposed LDO maintains a three-stage structure within the full load range. The proposed structure ensures the steady-state performance of LDO and achieves 0.017 mV/mA load regulation. The ATPS consumes little quiescent current at light load current condition, and the turn-on threshold of the ATPS can be adjusted by a current source. Once the value of current source is set, the turn-on threshold is also determined. A benefit of the proposed structure is that the LDO can be stable from 0 to 100 mA load current with a maximum 100 pF parasitic load capacitance and a 0.7 pF compensation capacitor. It also shows good figure of merit (FOM) without an extra transient enhanced circuit. For the maximum 100 mA load transient with 100 ns edge time, the undershoot and overshoot are less than 33 mV. The dropout voltage of the regulator is 200 mV with input voltage of 1.1 V. The total current consumption of the LDO was 24.6 μA at no load.
Keywords: adjustable threshold push–pull stage; fast-transient; fully integrated; load regulation; low voltage; low-dropout regulator; master–slave power transistors; system-on-chip (SoC).