Low Buffer Trapping Effects above 1200 V in Normally off GaN-on-Silicon Field Effect Transistors

Idriss Abid; Youssef Hamdaoui; Jash Mehta; Joff Derluyn; Farid Medjdoub

doi:10.3390/mi13091519

Low Buffer Trapping Effects above 1200 V in Normally off GaN-on-Silicon Field Effect Transistors

Micromachines (Basel). 2022 Sep 14;13(9):1519. doi: 10.3390/mi13091519.

Authors

Idriss Abid¹, Youssef Hamdaoui¹, Jash Mehta¹, Joff Derluyn², Farid Medjdoub¹

Affiliations

¹ IEMN (Institute of Electronics, Microelectronics and Nanotechnology), Avenue Poincaré, 59650 Lille, France.
² SOITEC-Belgium N.V., Kempische Steenweg 293, 3500 Hasselt, Belgium.

Abstract

We report on the fabrication and electrical characterization of AlGaN/GaN normally off transistors on silicon designed for high-voltage operation. The normally off configuration was achieved with a p-gallium nitride (p-GaN) cap layer below the gate, enabling a positive threshold voltage higher than +1 V. The buffer structure was based on AlN/GaN superlattices (SLs), delivering a vertical breakdown voltage close to 1.5 kV with a low leakage current all the way to 1200 V. With the grounded substrate, the hard breakdown voltage transistors at V_GS = 0 V is 1.45 kV, corresponding to an outstanding average vertical breakdown field higher than 2.4 MV/cm. High-voltage characterizations revealed a state-of-the-art combination of breakdown voltage at V_GS = 0 V together with low buffer electron trapping effects up to 1.4 kV, as assessed by means of substrate ramp measurements.

Keywords: GaN; high-electron-mobility transistor (HEMT); normally off.

Grants and funding

720527/Inrel-NPower