Optimization of Gate-All-Around Device to Achieve High Performance and Low Power with Low Substrate Leakage

Changhyun Yoo; Jeesoo Chang; Sugil Park; Hyungyeong Kim; Jongwook Jeon

doi:10.3390/nano12040591

Optimization of Gate-All-Around Device to Achieve High Performance and Low Power with Low Substrate Leakage

Nanomaterials (Basel). 2022 Feb 9;12(4):591. doi: 10.3390/nano12040591.

Authors

Changhyun Yoo¹, Jeesoo Chang², Sugil Park¹, Hyungyeong Kim¹, Jongwook Jeon¹

Affiliations

¹ Department of Electrical and Electronics Engineering, Konkuk University, Seoul 05029, Korea.
² Data and Information Tech. (DIT) Center, Samsung Electronics, Hwasung-Si 18448, Korea.

Abstract

In this study on multi-nanosheet field-effect transistor (mNS-FET)-one of the gate-all-around FETs (GAAFET) in the 3 nm technology node dimension-3D TCAD (technology computer-aided design) was used to attain optimally reduced substrate leakage from options including a punch-through-stopper (PTS) doping scheme and a bottom oxide (BO) scheme for bottom isolation, with the performance improvement being shown in the circuit-level dynamic operation using the mNS-FET. The PTS doping concentration requires a high value of >5 × 10¹⁸ cm^-3 to reduce gate induced drain leakage (GIDL), regardless of the presence or absence of the bottom isolation layer. When the bottom isolation is applied together with the PTS doping scheme, the capacitance reduction is larger than the on-state current reduction, as compared to when only the PTS doping concentration is applied. The effects of such transistor characteristics on the performance and capabilities of various circuit types-such as an inverter ring oscillator (RO), a full adder (FA) circuit, and a static random-access memory (SRAM)-were assessed. For the RO, applying BO along with the PTS doping allows the operating speed to be increased by 11.3% at the same power, or alternatively enables 26.4% less power consumption at the same speed. For the FA, power can be reduced by 6.45%, energy delay product (EDP) by 21.4%, and delay by 16.8% at the same standby power when BO and PTS are both applied. Finally, for the SRAM, read current (I_READ) increased by 18.7% and bit-line write margin (BWRM) increased by 12.5% at the same standby power. Through the circuit simulations, the Case 5 model (PTS doping concentration: 5.1 × 10¹⁸ cm^-3, with BO) is the optimum condition for the best device and circuit performance. These observations confirm that PTS and bottom isolation applications in mNS-FETs can be utilized to enable the superior characteristics of such transistors to translate into high performance integrated circuits.

Keywords: SRAM; bottom oxide; full adder; multi-nanosheet FET; punch-through-stopper; ring oscillator.

Abstract

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