Optimizing performance and yield of vertical GaN diodes using wafer scale optical techniques

James C Gallagher; Mona A Ebrish; Matthew A Porter; Alan G Jacobs; Brendan P Gunning; Robert J Kaplar; Karl D Hobart; Travis J Anderson

doi:10.1038/s41598-021-04170-2

Optimizing performance and yield of vertical GaN diodes using wafer scale optical techniques

Sci Rep. 2022 Jan 13;12(1):658. doi: 10.1038/s41598-021-04170-2.

Authors

James C Gallagher¹, Mona A Ebrish², Matthew A Porter³, Alan G Jacobs², Brendan P Gunning⁴, Robert J Kaplar⁴, Karl D Hobart⁵, Travis J Anderson⁵

Affiliations

¹ U.S. Naval Research Laboratory, 4555 Overlook Ave SW, Washington, DC, 20375, USA. james.gallagher@nrl.navy.mil.
² NRC Postdoc Fellow Residing at the U.S. Naval Research Laboratory, Washington, DC, 20375, USA.
³ Naval Postgraduate School, 1 University Dr, Monterey, CA, 93943, USA.
⁴ Sandia National Laboratories, MS 1086, PO Box 5800, Albuquerque, NM, 87185, USA.
⁵ U.S. Naval Research Laboratory, 4555 Overlook Ave SW, Washington, DC, 20375, USA.

Abstract

To improve the manufacturing of vertical GaN devices for power electronics applications, the effects of defects in GaN substrates need to be better understood. Many non-destructive techniques including photoluminescence, Raman spectroscopy and optical profilometry, can be used to detect defects in the substrate and epitaxial layers. Raman spectroscopy was used to identify points of high crystal stress and non-uniform conductivity in a substrate, while optical profilometry was used to identify bumps and pits in a substrate which could cause catastrophic device failures. The effect of the defects was studied using vertical P-i-N diodes with a single zone junction termination extention (JTE) edge termination and isolation, which were formed via nitrogen implantation. Diodes were fabricated on and off of sample abnormalities to study their effects. From electrical measurements, it was discovered that the devices could consistently block voltages over 1000 V (near the theoretical value of the epitaxial layer design), and the forward bias behavior could consistently produce on-resistance below 2 mΩ cm², which is an excellent value considering DC biasing was used and no substrate thinning was performed. It was found that high crystal stress increased the probability of device failure from 6 to 20%, while an inhomogeneous carrier concentration had little effect on reverse bias behavior, and slightly (~ 3%) increased the on-resistance (R_on). Optical profilometry was able to detect regions of high surface roughness, bumps, and pits; in which, the majority of the defects detected were benign. However a large bump in the termination region of the JTE or a deep pit can induce a low voltage catastrophic failure, and increased crystal stress detected by the Raman correlated to the optical profilometry with associated surface topography.