Novel Program Scheme of Vertical NAND Flash Memory for Reduction of Z-Interference

Su-In Yi; Jungsik Kim

doi:10.3390/mi12050584

Novel Program Scheme of Vertical NAND Flash Memory for Reduction of Z-Interference

Micromachines (Basel). 2021 May 20;12(5):584. doi: 10.3390/mi12050584.

Authors

Su-In Yi^{1

2}, Jungsik Kim^{3

4}

Affiliations

¹ Department of Electrical and Computer Engineering, Texas A&M University, College Station, TX 77843, USA.
² Samsung Electronics, Hwasung 18448, Kyeonggi, Korea.
³ Department of Electrical Engineering, Gyeongsang National University, Jinju 52828, Gyeongnam, Korea.
⁴ Engineering Research Institute (ERI), Gyeongsang National University, Jinju 52828, Gyeongnam, Korea.

Abstract

Minimizing the variation in threshold voltage (V_t) of programmed cells is required to the extreme level for realizing multi-level-cells; as many as even 5 bits per cell recently. In this work, a recent program scheme to write the cells from the top, for instance the 170th layer, to the bottom, the 1st layer, (T-B scheme) in vertical NAND (VNAND) Flash Memory, is investigated to minimize V_t variation by reducing Z-interference. With the aid of Technology Computer Aided Design (TCAD) the Z-Interference for T-B (84 mV) is found to be better than B-T (105 mV). Moreover, under scaled cell dimensions (e.g., L_g: 31→24 nm), the improvement becomes protruding (T-B: 126 mV and B-T: 162 mV), emphasizing the significance of the T-B program scheme for the next generation VNAND products with the higher bit density.

Keywords: NAND flash memory; Technology Computer Aided Design (TCAD) simulation; disturbance; interference; non-volatile memory (NVM); program.

Grants and funding

2020R1G1A1099554/National Research Foundation of Korea