CMOS microelectrode arrays (MEAs) can record electrophysiological activities of a large number of neurons in parallel but only extracellularly with low signal-to-noise ratio. Patch clamp electrodes can perform intracellular recording with high signal-to-noise ratio but only from a few neurons in parallel. Recently we have developed and reported a neuroelectronic interface that combines the parallelism of the CMOS MEA and the intracellular sensitivity of the patch clamp. Here, we report the design and characterization of the CMOS integrated circuit (IC), a critical component of the neuroelectronic interface. Fabricated in 0.18-μm technology, the IC features an array of 4,096 platinum black (PtB) nanoelectrodes spaced at a 20 μm pitch on its surface and contains 4,096 active pixel circuits. Each active pixel circuit, consisting of a new switched-capacitor current injector--capable of injecting from ±15 pA to ±0.7 μA with a 5 pA resolution--and an operational amplifier, is highly configurable. When configured into current-clamp mode, the pixel intracellularly records membrane potentials including subthreshold activities with ∼23 μVrms input referred noise while injecting a current for simultaneous stimulation. When configured into voltage-clamp mode, the pixel becomes a switched-capacitor transimpedance amplifier with ∼1 pArms input referred noise, and intracellularly records ion channel currents while applying a voltage for simultaneous stimulation. Such voltage/current-clamp intracellular recording/stimulation is a feat only previously possible with the patch clamp method. At the same time, as an array, the IC overcomes the lack of parallelism of the patch clamp method, measuring thousands of mammalian neurons in parallel, with full-frame intracellular recording/stimulation at 9.4 kHz.
Keywords: current clamp; extracellular recording; integrated circuits; intracellular recording; microelectrode array; nano-bio interface; nanoelectrode array; neurobiology; neurons; switched capacitor; voltage clamp.