A Multi-Core Object Detection Coprocessor for Multi-Scale/Type Classification Applicable to IoT Devices

Peng Xu; Zhihua Xiao; Xianglong Wang; Lei Chen; Chao Wang; Fengwei An

doi:10.3390/s20216239

A Multi-Core Object Detection Coprocessor for Multi-Scale/Type Classification Applicable to IoT Devices

Sensors (Basel). 2020 Oct 31;20(21):6239. doi: 10.3390/s20216239.

Authors

Peng Xu¹, Zhihua Xiao¹, Xianglong Wang¹, Lei Chen², Chao Wang^{3

4}, Fengwei An^{1

2

5}

Affiliations

¹ School of Microelectronics, Southern University of Science and Technology, Shenzhen 518055, China.
² Pengcheng Laboratory, Shenzhen 518055, China.
³ Department of Integrated Circuit Engineering, Huazhong University of Science and Technology, Wuhan 430074, China.
⁴ Wuhan National Laboratory for Optoelectronics, Wuhan 430074, China.
⁵ Engineering Research Center of Integrated Circuits for Next-Generation Communications, Ministry of Education, Southern University of Science and Technology, Shenzhen 518055, China.

Abstract

Power efficiency is becoming a critical aspect of IoT devices. In this paper, we present a compact object-detection coprocessor with multiple cores for multi-scale/type classification. This coprocessor is capable to process scalable block size for multi-shape detection-window and can be compatible with the frame-image sizes up to 2048 × 2048 for multi-scale classification. A memory-reuse strategy that requires only one dual-port SRAM for storing the feature-vector of one-row blocks is developed to save memory usage. Eventually, a prototype platform is implemented on the Intel DE4 development board with the Stratix IV device. The power consumption of each core in FPGA is only 80.98 mW.

Keywords: block-level once sliding detection window; histogram of oriented gradient; multi-shape detection-window; object-detection coprocessor; power efficiency; support vector machine.