A novel CMOS-process-compatible high-holding voltage silicon-controlled rectifier (HHV-SCR) for electrostatic discharge (ESD) protection is proposed and demonstrated by simulation and transmission line pulse (TLP) testing. The newly introduced hole (or electron) recombination region H-RR (or E-RR) not only recombines the minority carrier in parasitic PNP (or NPN) transistor base by N+ (or P+) layer, but provides the additional recombination to eliminate the surface avalanche carriers by newly added P+ (or N+) layer in H-RR (or E-RR), which brings about a further improvement of holding voltage (Vh). Compared with the measured Vh of 1.8 V of low-voltage triggered silicon-controlled rectifier (LVTSCR), the Vh of HHV-SCR can be increased to 8.1 V while maintaining a sufficiently high failure current (It2 > 2.6 A). An improvement of over four times in the figure of merit (FOM) is achieved.
Keywords: Electrostatic discharge (ESD); Holding voltage (V h); Latch-up; Silicon-controlled rectifier (SCR); Transmission line pulse (TLP).