For some years now, the ever continuing dimensional scaling has no longer been considered to be sufficient for the realization of advanced CMOS devices. Alternative approaches, such as employing new materials and introducing new device architectures, appear to be the way to go forward. A currently hot approach is to employ ferroelectric materials for obtaining a positive feedback in the gate control of a switch. This work elaborates on two device architectures based on this approach: the negative-capacitance and the piezoelectric field-effect transistor, i.e., the NC-FET (negative-capacitance field-effect transistor), respectively π -FET. It briefly describes their operation principle and compares those based on earlier reports. For optimal performance, the adopted ferroelectric material in the NC-FET should have a relatively wide polarization-field loop (i.e., "hard" ferroelectric material). Its optimal remnant polarization depends on the NC-FET architecture, although there is some consensus in having a low value for that (e.g., HZO (Hafnium-Zirconate)). π -FET is the piezoelectric coefficient, hence its polarization-field loop should be as high as possible (e.g., PZT (lead-zirconate-titanate)). In summary, literature reports indicate that the NC-FET shows better performance in terms of subthreshold swing and on-current. However, since its operation principle is based on a relatively large change in polarization the maximum speed, unlike in a π -FET, forms a big issue. Therefore, for future low-power CMOS, a hybrid solution is proposed comprising both device architectures on a chip where hard ferroelectric materials with a high piezocoefficient are used.
Keywords: CMOS; MOS devices; ferroelectrics; field-effect transistor; negative-capacitance; piezoelectrics; power consumption.