Next generation implantable neural interfaces are targeting devices with mm-scale form factors that are freely floating and completely wireless. Scalability to more recording (or stimulation) channels will be achieved through distributing multiple devices, instead of the current approach that uses a single centralized implant wired to individual electrodes or arrays. In this way, challenges associated with tethers, micromotion, and reliability of wiring is mitigated. This concept is now being applied to both central and peripheral nervous system interfaces. One key requirement, however, is to maximize specific absorption rate (SAR) constrained achievable wireless power transfer efficiency (PTE) of these inductive links with mm-sized receivers. Chip-scale coil structures for microsystem integration that can provide efficient near-field coupling are investigated. We develop near-optimal geometries for three specific coil structures: in-CMOS, above-CMOS (planar coil post-fabricated on a substrate), and around-CMOS (helical wirewound coil around substrate). We develop analytical and simulation models that have been validated in air and biological tissues by fabrications and experimental measurements. Specifically, we prototype structures that are constrained to a 4 mm 4 mm silicon substrate, i.e., the planar in-/above-CMOS coils have outer diameters 4 mm, whereas the around-CMOS coil has an inner diameter of 4 mm. The in-CMOS and above-CMOS coils have metal film thicknesses of 3- m aluminium and 25- m gold, respectively, whereas the around-CMOS coil is fabricated by winding a 25-m gold bonding wire around the substrate. The measured quality factors (Q) of the mm-scale Rx coils are 10.5 @450.3 MHz (in-CMOS), 24.61 @85 MHz (above-CMOS), and 26.23 @283 MHz (around-CMOS). Also, PTE of 2-coil links based on three types of chip-scale coils is measured in air and tissue environment to demonstrate tissue loss for bio-implants. The SAR-constrained maximum PTE measured (together with resonant frequencies, in tissue) are 1.64% @355.8 MHz (in-CMOS), 2.09% @82.9 MHz (above-CMOS), and 3.05% @318.8 MHz (around-CMOS).