Synchronous OEIC Integrating Receiver for Optically Reconfigurable Gate Arrays

Carlos Sánchez-Azqueta; Bernhard Goll; Santiago Celma; Horst Zimmermann

doi:10.3390/s16060761

Synchronous OEIC Integrating Receiver for Optically Reconfigurable Gate Arrays

Sensors (Basel). 2016 May 25;16(6):761. doi: 10.3390/s16060761.

Authors

Carlos Sánchez-Azqueta^{1

2}, Bernhard Goll³, Santiago Celma⁴, Horst Zimmermann⁵

Affiliations

¹ Institute of Electrodynamics, Microwave and Circuit Engineering, Vienna University of Technology, Gußhausstraße 25/354, Vienna 1040, Austria. csanaz@unizar.es.
² Group of Electronic Design, Aragón Institute of Engineering Research, Universidad de Zaragoza, Pedro Cerbuna 12, Zaragoza 50009, Spain. csanaz@unizar.es.
³ Institute of Electrodynamics, Microwave and Circuit Engineering, Vienna University of Technology, Gußhausstraße 25/354, Vienna 1040, Austria. bernhard.goll@tuwien.ac.at.
⁴ Group of Electronic Design, Aragón Institute of Engineering Research, Universidad de Zaragoza, Pedro Cerbuna 12, Zaragoza 50009, Spain. scelma@unizar.es.
⁵ Institute of Electrodynamics, Microwave and Circuit Engineering, Vienna University of Technology, Gußhausstraße 25/354, Vienna 1040, Austria. horst.zimmermann@tuwien.ac.at.

Abstract

A monolithically integrated optoelectronic receiver with a low-capacitance on-chip pin photodiode is presented. The receiver is fabricated in a 0.35 μm opto-CMOS process fed at 3.3 V and due to the highly effective integrated pin photodiode it operates at μW. A regenerative latch acting as a sense amplifier leads in addition to a low electrical power consumption. At 400 Mbit/s, sensitivities of -26.0 dBm and -25.5 dBm are achieved, respectively, for λ = 635 nm and λ = 675 nm (BER = 10(-9) ) with an energy efficiency of 2 pJ/bit.

Keywords: integrated optoelectronics; integrated pin photodiode; integrating receiver.