Accurate dynamic power estimation for CMOS combinational logic circuits with real gate delay model

Omnia S Fadl; Mohamed F Abu-Elyazeed; Mohamed B Abdelhalim; Hassanein H Amer; Ahmed H Madian

doi:10.1016/j.jare.2015.02.006

Accurate dynamic power estimation for CMOS combinational logic circuits with real gate delay model

J Adv Res. 2016 Jan;7(1):89-94. doi: 10.1016/j.jare.2015.02.006. Epub 2015 Mar 2.

Authors

Omnia S Fadl¹, Mohamed F Abu-Elyazeed¹, Mohamed B Abdelhalim², Hassanein H Amer³, Ahmed H Madian⁴

Affiliations

¹ Electronics and Communications Department, Faculty of Engineering, Cairo University, University Street, P.O. Box 268, Giza 12316, Egypt.
² College of Computing and Information Technology (CCIT), AASTMT, P.O. Box 2033, El Moshir Ismail st., Heliopolis, Cairo, Egypt.
³ Electronics and Communications Engineering Department, American University in Cairo, P.O. Box 74, New Cairo 11835, Egypt.
⁴ Radiation Engineering Department, NCRRT, 3 Ahmed El Zomor St., P.O. Box 29, Cairo 11787, Egypt.

Abstract

Dynamic power estimation is essential in designing VLSI circuits where many parameters are involved but the only circuit parameter that is related to the circuit operation is the nodes' toggle rate. This paper discusses a deterministic and fast method to estimate the dynamic power consumption for CMOS combinational logic circuits using gate-level descriptions based on the Logic Pictures concept to obtain the circuit nodes' toggle rate. The delay model for the logic gates is the real-delay model. To validate the results, the method is applied to several circuits and compared against exhaustive, as well as Monte Carlo, simulations. The proposed technique was shown to save up to 96% processing time compared to exhaustive simulation.

Keywords: CMOS combinational logic circuits; Dynamic power estimation; Logic pictures; Real-delay model; Switching activity; Toggle rate.