This paper considers the basic Lazzaro winner-take-all analog computing circuit with N current inputs, N voltage outputs, and a bias current. Motivated by low-power applications, we find a mathematical accurate model of the network when all MOS devices remain inside the subthreshold region all along the transient. This involves analytical inequalities relating the range of admissible input currents to transistor parameters, to supply voltage, and to bias current. The restrictions are sufficiently weak to allow extra demands of functionality or performance. The technical novelty here is that by a slight cut of the maximal subthreshold domain and by choosing proper coordinates, we get a ordinary differential equation invariance problem on a rectangle of ℜN+1 space which is analytically tractable. A more precise localization of the asymptotically stable steady state inside the region of interest is also inferred. Although the work is mainly theoretical, an effort to infer simple, interpretable formulas useful for synthesis has been made. The results are numerically verified and their feasibility is discussed in detail. The subject matter is new and it is worth extending it to larger classes of circuits with regional behavior.