Interface Passivation and Trap Reduction via a Solution-Based Method for Near-Zero Hysteresis Nanowire Field-Effect Transistors

ACS Appl Mater Interfaces. 2015 Oct 14;7(40):22115-20. doi: 10.1021/acsami.5b07140. Epub 2015 Sep 29.

Abstract

In this letter, we demonstrate a solution-based method for a one-step deposition and surface passivation of the as-grown silicon nanowires (Si NWs). Using N,N-dimethylformamide (DMF) as a mild oxidizing agent, the NWs' surface traps density was reduced by over 2 orders of magnitude from 1×10(13) cm(-2) in pristine NWs to 3.7×10(10) cm(-2) in DMF-treated NWs, leading to a dramatic hysteresis reduction in NW field-effect transistors (FETs) from up to 32 V to a near-zero hysteresis. The change of the polyphenylsilane NW shell stoichiometric composition was confirmed by X-ray photoelectron spectroscopy analysis showing a 35% increase in fully oxidized Si4+ species for DMF-treated NWs compared to dry NW powder. Additionally, a shell oxidation effect induced by DMF resulted is a more stable NW FET performance with steady transistor currents and only 1.5 V hysteresis after 1000 h of air exposure.

Keywords: DMF; XPS; field-effect transistor; hysteresis; interface passivation; interface trap reduction; nanowire interface; silicon nanowires.

Publication types

  • Letter
  • Research Support, Non-U.S. Gov't
  • Research Support, U.S. Gov't, Non-P.H.S.