In recent years, limitations in optical lithography have challenged the cost-effective manufacture of nano- and microelectronic chips. Spatially regular designs have been introduced to improve manufacturability. However, regular designed layouts typically require an interference step followed by a trim step. These multiple steps increase cost and reduce yield. In the present work, Pattern-Integrated Interference Lithography (PIIL) is introduced to address this problem. PIIL is the integration of interference lithography and superposed pattern mask imaging, combining the interference and the trim into a single-exposure step. Example PIIL implementations and experimental demonstrations are presented. The degrees of freedom associated with the source, pattern mask, and Fourier filter designs are described.