Through silicon via (TSV) technology is becoming a mainstream method of building 3-dimensional integrated circuits (3D IC). In particular, TSV Cu CMP is a critical process to remove excess Cu and makes a planar surface which requires a removal rate higher than 5 microm/min and a dishing lower than 0.3 microm. This paper focuses on the development of a new self-alignment method using dimples on the TSV Cu back surface. We tried to find an application potential of a bump-dimple structure for self alignment using a pretest tool of a solder ball array structure. Chemical-mechanical planarization (CMP) aided dimple etching is carefully studied as a key solution for deep and uniform dimple formation. The experiment shows that CMP is an excellent process to generate a clean oxide surface and a clear dishing on the Cu TSV, resulting in a seed for etching. Finally, etching realizes a uniform dimple depth of 7 microm to 9 microm in spite of changes of via diameter from 10 microm to 50 microm after only 15 sec etching.