In this paper, an explicit and continuous analytical model including interfacial hot-carrier effects is developed for a deep submicron Gate All Around (GAA) MOSFETs. Explicit analytical expressions of the surface potential, drain current and transconductance are given for all operating modes. Exploiting this new device model, we have found that the incorporation of a high-k layer, Gate Stack (GS), between oxide region and gate metal leads to drain current enhancement, improved transconductance parameter and enhanced interfacial hot-carrier immunity. The developed approaches are verified and validated by the good agreement found with the 2D numerical simulations for wide range of device parameters and bias conditions. GS GAA MOSFET design can alleviate the critical problem and further improve the immunity of hot-carrier effects of GAA MOSFET-based circuits in the deep submicron working domain.