The effects of active layer thickness and device dimensions on nanometal-induced crystallization (nano-MIC) were studied to determine the electrical characteristics of the polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with bottom-gate structures. The nano-MIC poly-Si film was obtained via deposition of a 0.4-nm-thick Ni film on the amorphous silicon layer and subsequent annealing at 550 degrees C for 0.5 to 8 h. The EDS revealed a approximately 0.1% Ni concentration in the poly-Si film. The cross-sectional TEM image shows the vertical-grain growth mechanism, where the bottom side of the grain exhibits a larger crytalline area than the top side. Therefore, the field effect mobility of the bottom-gate poly-Si TFTs increases with increased active-amorphous-silicon (a-Si) thickness. Furthermore, the mobility increases when the device dimensions are scaled down. A mechanism for explaining such phenomenon in relation to the nano-MIC bottom-gate poly-Si TFTs was also proposed.