Continuous Interleaved Sampling (CIS) is one of the most useful and famous speech processing strategies used in Cochlear Implant speech processors. However, algorithm realization in hardware is a laborious task due to high computation cost of the algorithm. Real-time issues and low-power design demands an optimized realization of algorithm. This paper proposes two techniques to cut the computation cost of CIS by using polyphase filters and by implementing the complete algorithm in frequency domain. About 70% reduction in computation cost can be achieved by using multi-rate, multistage filters; whereas computation cost decreases by a factor of five when the whole algorithm is implemented in frequency domain. Evaluation of the algorithm is done by a laboratory designed algorithm development and evaluation platform. Algorithm flow diagrams and their computation details have been given for comparison. Utilizing the given techniques can remarkably reduce the processor load without any compromise on quality.